90 lines
3.8 KiB
C++
90 lines
3.8 KiB
C++
//==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API of helper functions used throughout the
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/// GlobalISel pipeline.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#define LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#include "llvm/ADT/StringRef.h"
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namespace llvm {
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class MachineFunction;
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class MachineInstr;
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class MachineOptimizationRemarkEmitter;
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class MachineOptimizationRemarkMissed;
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class MachineRegisterInfo;
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class MCInstrDesc;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetPassConfig;
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class TargetRegisterInfo;
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class TargetRegisterClass;
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class Twine;
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class ConstantFP;
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/// Try to constrain Reg to the specified register class. If this fails,
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/// create a new virtual register in the correct class and insert a COPY before
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/// \p InsertPt. The debug location of \p InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainRegToClass(MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI,
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MachineInstr &InsertPt, unsigned Reg,
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const TargetRegisterClass &RegClass);
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/// Try to constrain Reg so that it is usable by argument OpIdx of the
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/// provided MCInstrDesc \p II. If this fails, create a new virtual
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/// register in the correct class and insert a COPY before \p InsertPt.
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/// This is equivalent to constrainRegToClass() with RegClass obtained from the
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/// MCInstrDesc. The debug location of \p InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainOperandRegClass(const MachineFunction &MF,
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const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI,
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MachineInstr &InsertPt, const MCInstrDesc &II,
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unsigned Reg, unsigned OpIdx);
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/// Check whether an instruction \p MI is dead: it only defines dead virtual
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/// registers, and doesn't have other side effects.
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bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
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/// Report an ISel error as a missed optimization remark to the LLVMContext's
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/// diagnostic stream. Set the FailedISel MachineFunction property.
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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MachineOptimizationRemarkMissed &R);
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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const char *PassName, StringRef Msg,
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const MachineInstr &MI);
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Optional<int64_t> getConstantVRegVal(unsigned VReg,
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const MachineRegisterInfo &MRI);
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const ConstantFP* getConstantFPVRegVal(unsigned VReg,
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const MachineRegisterInfo &MRI);
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/// See if Reg is defined by an single def instruction that is
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/// Opcode. Also try to do trivial folding if it's a COPY with
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/// same types. Returns null otherwise.
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MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg,
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const MachineRegisterInfo &MRI);
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} // End namespace llvm.
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#endif
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